View MICRF219AAYQS_9017935.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

300mhz to 450mhz ask receiver w rssi, auto-poll, bit-che micrf219 ith ck and squelch not recommended refer to micrf219a for new designs qwikradio is a registered trademark of micrel, inc. micrel inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com june 2011 m9999-060811 (408) 944-0800 3 0 s r l mode, fully awakes the receiver the microcontroller once a valid number of bits are detected. during normal operation an optional squelch feature disa bles the data output until valid bits are detected. an optional desense feature reduces gain by 6db to 42db, distancing the receiver from distantly placed, undesired transmitters. dbm sensitivity at 1kbps with 1% ber data rates up to 10kbps at 433.92mhz output ange 315mhz (continuous receive) hz (continuous receive) in shutdown mode ling (sleep mode, current < 0.1ma) ck in auto-poll mode able 6db to 42db desense data output squelch until valid bits detected ? 1 kag m x 6.0mm) ? 40 c te e ? evaluation board qr219bpf available ordering information part number temperature range package general description the micrf219 is a 300mhz to 450mh heterodyne, image-reject, rf receiver with gain control, ook/ask dem odulator and a output. the device integrates auto-poll, z super- ? C110 automatic ? supports nalog rssi ? 25db image-re valid bit-check, ject mixer squelch, and desense features. it only crystal and a minimum number of external c to implement. it is ideal for low-cost, low-po tpms, and remote actuation applications. the micrf219 achieves ? 110dbm sensitivit rate of 1kbps (manchester encoded). four d filter bandwidths are selectable in binary 1625hz to 13khz at 433mhz, allowing the support data rates to 10kbps. the device ope a supply voltage of 3.0v to 3.6v, and consum of supply current at 315mhz and 6.0ma at 4 a shutdown mode reduces supply current to auto-polling feature allows the micrf219 to poll for user defined periods, thus furthe requires a ? no if filter required omponents ? 60db analog rssi wer, rke, ? 3.0v to 3.6v supply voltage r y at a data at emodulator ? 6.0ma supply current at 434m steps from ? 0.5ua supply current device to ? optional auto-pol rates from ? optio es 4.0ma nal valid bit-che ? optional programm 3.92mhz. .5 ? optional ua. the leep and reducing ? supply current. the valid bit-check feature, when ? 2kv hbm esd rating enabled in auto-pol and sends bits to features ? 4.0ma supply current 6-pin qsop pac e (4.9m c to +105 mperature rang micrf219ayqs ? 40 c to +105 c 16-pin qsop _______________________________________________________________________________________________ typical application downloaded from: http:///
micrel micrf219 june 2011 2 m9999-060811 (408) 944-0800 pin configuration 1 ro1 gndrf ant gndrf vdd sq sel0 7 shdn 16 ro2 sclkrssi cagc cth sel1 do gnd 1514 13 12 11 10 9 23 4 5 6 8 micrf219ayqs pin descript sop n n ion 16-pin q pi ame pin function 1 ro ut: reference resonator input connection to pierce oscillator stage. may also aximum. internal e of 7pf to gnd during normal operation. 1 be driven by external reference signal of 200mvp -p to 1.5v p-p amplitude m capacitanc reference oscillator inp 2 gndrf negative supply connection associated with ant rf input. 3 ant antenna. inte rnally ac coupled. it is recommended a matching on. network with an inductor-to-rf ground be used to improve esd protecti antenna input: rf signal input from 4 nd g rf ground connection for ant rf input. 5 d lose to the v d positive supply connection for all chip functions. by pass with 0.1f capacitor located as c vdd pin as possible. 6 sq l- up pulls the logic-input high when the device is vel signal is applied the enabled. bit d17 sets whether squelch is enabled or disabled when a logic-le sq pin. see squelch enable truth-table on page squelch control logic-level input. an internal pul 7 e a typical) when not in dwidth lsb when serial ined in sleep mode. s l0 demodulator filter bandwidth select logic-level in put. internal pull- up (3u shutdown or sleep mode. used in conjunction with sel1 to control d3 ban interface contains default setting. it does not need to be def 8 hd logic-level high places in low-power shutdown mode. an internal pull-up pulls the logic input high. s n shutdown control logic-level input. a logic-level lo w enables the device. a the device 9 ng d negative supply connection for all chip functions except for rf input. 10 do ble. sed as a cmos schmitt input utdown and sleep modes. a current limited cmos output during normal operation th is pin is also u for serial interface data. a 25k ? pull-down is present when device is in sh data input and output. demodulated data output. may be blanked until bit checking test is accepta 11 sel1 pical) pull-up when not in shutdown or sleep mode. used in conjunction with sel0, to control d4 bandwidth msb, when serial interface contains default setting. it does not need to be defined in sl de. demodulator filter bandwidth select logic-level input: internal (3ua ty eep mo 12 cth demodulation threshold voltage integration capacitor . capacitor-to-gnd sets the settling time for the demodulation data slicing level. values above 1nf are recommended and should be optimized for data rate and data profile. 13 cagc agc filter capacitor. a capacitor, normally greater than 0.47 f, is connected from this pin-to-gnd 14 rssi received signal strength indication (o utput): output is from a swit ched capacitor integrating op amp with 220 ? typical output impedance. 15 sclk serial interface input clock. cmos schmitt input. a 25k ? pull-down is present when device is in shutdown mode. 16 ro2 reference resonator connection. internal c apacitance of 7pf to gnd dur ing normal operation. downloaded from: http:///
micrel micrf219 june 2011 3 m9999-060811 (408) 944-0800 . . . storage temperature (ts) ...................... -65oc t +150c wer ......................... +10dbm .. .. . .............+3.0v to +3.6v ......... C40c to +105c ............................. 3.6v ....................... ? 20dbm receive modulation duty cycle (6) .................... 20~80% frequency range........................... 300mhz to 450mhz ica character for v dd = 3 c th = 0.1f rx = z unle rwise noted. bold values indicate C40 c C t a C 105 c. ded), re ence oscillator frequency = 13.52127mhz. on min. typ. max. units absolute maximum ratings (1) supply voltage (vdd) ..................................... .......... +5v supply voltage (vdd) ................ input voltage. .................................................. .......... +5v ambient temperature (t a ) ........ junction temperature ....................... ............. . .....+150oc input voltage (vin) .................... lead temperature (solde ring, 10sec .) ................ ...300c maximum input rf power......... . o maximum receiver input po (3) eds rating ..... .......................... ............... 2kv hbm l operating ratings (2) electr istics specifications apply .3v, gnd = 0v, c agc = 4.7f, , f 433.92 mh ss othe 1kbps data rate (manchester enco fer parameter conditi continuous operation, f rx = 315mhz 4.0 operating supply current ntinuous operation, f rx = 433.92mh 6.0 ma co z shutdown current 0.15 a receiver image rejection 25 db f rx = 315mhz 0.86 1 st if center frequency = 433.92mhz 1.2 mhz f rx f rx = 315 mhz, 50 ? ber=10 -2 ? 110 receiver sensitivity @ 1 (note 4) kbps f = 433.92mhz, 50 ? ber=10 ? 110 dbm rx -2 f rx = 315mhz 235 if bandwidth f rx = 433.92mhz 330 khz f rx = 315mhz 2 C j235 3 antenna input impedance rx hz 74 ? f = 433.92m 19 C j1 receive modulation duty cyc 20 80 % le note 5 agc attack / decay ratio t attack / t decay 0.1 agc pin leakage current t a = 25oc t a = + 105oc 30 800 na na rf in @ ? 40dbm 1.15 v agc dynamic range rf in @ ? 100dbm 1.70 v reference oscillator f rx = 315 mhz, crystal load cap = 10pf 9.81563 reference oscillator frequency f rx = 433.92 mhz, crystal load cap = 10pf 2127 mhz 13.5 reference oscillator input impedance ro1 1.6 k ? reference oscillator bias voltage ro2 1.15 v downloaded from: http:///
micrel micrf219 june 2011 4 m9999-060811 (408) 944-0800 apply for v dd d = 0v, c agc = 4.7f, c th = 0.1 x = 433.92 m le erwise noted. bold values c. 1kbps data rate (manchester encoded), refer ator frequenc .52127mhz. on typ. max. units electrical characteristics (continued) specifications = 3.3v, gn f, f r hz un ss oth = 13 indicate C40 c C t a C 105 ence oscill y parameter conditi min. reference oscillator input range 0.2 1.5 v p-p reference oscillator sourc ) = 0v 300 a e v(refosc current demodulator f refosc = 9.81563 mhz 165 cth source impedance z 120 k ? f refosc = 13.52127mh cth leakage current t a = 25oc t = +105oc a 2 800 na demodulator filter bandwid , see application section 0 9400 hz th programmable @ 315mhz 117 demodulator filter bandwi @ 434mhz e, see application section 625 13000 hz dth programmabl 1 digital / control functions do pin output current dd sink @ 0.2 v dd 260 600 a as output source @ 0.8 v output rise and fall times ci = 15pf, pin do, 10-90% 2 sec input high voltage pins sclk, do (as input), shdn,sel0, sel1,sq 0.8v dd v input low voltage pins sclk, do (as input), shdn, sel0, 0.2v dd v sel1,sq output voltage high do 0.8v dd v output voltage low do 0.2v dd v rssi ? 100dbm 0.4 rssi dc output voltage range ? 40dbm 2.0 v rssi response slope ? 110dbm to -40dbm 25 mv/db rssi output current 400 a rssi output impedance 250 ? rssi response time 50% data duty cycle, input power to antenna = - 20dbm 0.3 sec notes: eeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to fu nction outside of its operating rating. 3. device is esd sensitive. use appropriate esd precautions . exceeding the absolute maximu m rating may damage the device. 4. sensitivity is defined as the average signal level measured at the input necessary to achieve 10 -2 ber (bit error rate). the input signal is defined as a return-to-zero (rz) waveform with 50% average dut y cycle (manchester encoded) at a data rate of 1kbps. 5. when data burst does not contain preamble, duty cycle is defined as total duty cycle, including any quiet time between dat a bursts. when data bursts contain preamble sufficient to charge the slice level on capacitor c th , then duty cycle is the effective duty cycle of the burst alone. [for example, 100msec burst with 50% duty cycle, and 100msec quiet time between bursts. if burst includes preamble, duty cycle i s t on /(t on +t off )= 50%; without preamble, duty cycle is t on /(t on + t off + t quiet ) = 50msec/(200msec)=25%. t on is the (average number of 1s/burst) bit time, and t off = (t burst C t on .) 1. exc downloaded from: http:///
micrel micrf219 june 2011 5 m9999-060811 (408) 944-0800 typical characteristics -120 432.9 433.1 433.3 433.5 433.7 433.9 434.1 434.3 434.5 434.7 434.9 frequency (mhz) -110 -100 -90 -80 -70 -60 -50 selectivity (dbm) -40c +105c +20c 433mhz selectivity and bandwidth by different temps. 4 4.5 5 5.5 6 6.5 7 3.0 3.1 3.2 3.3 3.4 3.5 3.6 current (ma) voltage (v) 433.92mhz v/i by temperatures 20c -40c 105c downloaded from: http:///
micrel micrf219 june 2011 6 m9999-060811 (408) 944-0800 functional diagram synthesizer control logic if amp lna mixer mixer control logic control logic control logic -f f i image reject filter desense detector ook demodulator uhf downcoverter reference and control autopoll programmable filter bitcheck wake-up squelch sleep timer sleep oscillator reference oscillator agc control rssi rssi do cagc cth slicer slice level do do' do' f lo figure 1. simplified block diagram downloaded from: http:///
micrel micrf219 june 2011 7 m9999-060811 (408) 944-0800 iagram, shown in figure 1, ctur e of the micrf219 receiver. ub-blocks: tor ( ditional five components nce; a power supply d omponents for the matching b nts: lna, d t f e and synthesizer n by quadra re lock. e place l to a ow i the if a scillat e cy via a er with a fully integrated loop filter. image-reject filter and band-pass filter ports of the mixer produce quadrature-down converted if signals. these if signals are low-pass filtered to remove higher frequency products prior to the image reject filter where they are combined to reject the image frequencies. the if signal then passes through a third order band pass filter. the if center frequency is 1.2mhz. the if bw is 330khz @ 433.92mhz. this varies with rf operating frequency. the if bw can be calculated via direct scaling: bw if if@433.92 mhz functional description the simplified block d illustrates the basic stru it is made up of four s ? uhf down-converter ? ook demodula ? reference and control logic ? auto-poll circuitry outside the device, the micrf219 receiver re three components to operate: two capacitors cagc) and the reference frequency device quires just cth, and (usually a quartz crystal). an ad to improve performa are used ecoupling network, and-pass capacitor, two c and two components for the pre-selector filter. receiver operation uhf downconverter the uhf down-converter has six compone mixers, synthesizer, image re ject filter, ban pass filter and if amp. lna the rf input signal is ac-coupled into the ga the grounded source lna input stage. the cascoded nmos amplifier. t he amplified r then fed to the rf ports of two double balanc mixers e circuit of lna is a signal is d mixers. the lo ports of the mixers are drive tu local oscillator outputs from the synthesizer b local oscillator signal from the synthesizer is the low side of the desired rf signa suppression of the image frequency at tw frequency below the wanted signal. the loc is set to 32 times the crystal reference frequ phase-locked loop synthesiz th d on ll ce l o or n the if = bw ? ? ? ? (mhz) freq operating these filters side the micrf219. r filt rolled amplifier stages ts proper level for mprised of detector, , slicer, and agc -pass filter detector removing the t detection, the signal . the programmable ss filter furthe r enhances the baseband information. there are four programmable low-pass ttings: 1625hz, 3250hz, 6500hz, 13000hz for 433.92mhz operation. low pass filter bw will vary with rf operating frequency. filter bw values can be . see equation below w operating freq = bw @433.92mhz * ? ? 433.92 are fully integrated in ering, four active gain cont afte enhance the if signal to i demodulation. ook demodulator the demodulator section is co programmable low pass filter comparator. detector and programmable low the demodulation starts with the carrier from the if signal. pos becomes base band information low-pa filter bw se easily calculated by direct scaling for filter bw calculation: b ?? ? ?? ? o 433.92 (mhz) freq perating very important to choose filter setting that fits best e in data rate to minimize data distortion. em 3000hz @ 433.92mhz as default nd sel1 pins are floating). the hardware set by external pins sel0 and sel1. sel0 sel1 demod bw (@ 434mhz) it is th tended d (assu od bw is set at 1 ming both sel0 a low pass filter can be 0 0 1625hz 1 0 3250hz 0 1 6500hz 1 1 13000hz - default table 1. demodulation bw selection downloaded from: http:///
micrel micrf219 june 2011 8 m9999-060811 (408) 944-0800 data cer ros based on cap itor. tal da . the slicing threshold is default at 50%. the ing threshold n b serial programming through register d5 and d5 d slicer and slicing level the signal, prior to the slicer, is still am. the converts the am signal into ones and ze sli the threshold voltage built up in the cth after the slicer, the signal is ask or ook digi ac ta slic ca e set via d6. 6 slicing level 1 0 l 30% slice leve 0 1 slice level 40% 1 1 slice level 50% - default 0 0 slice level 60% agc comparator the agc comparator monitors the signal from the output of the programmable low when the output signal is less than 750mv th 1.5a amplitude ass filter. -p current is sourced into the external cagc tor. when the output signal is greater th th cagc he ca a ig designed to reduce the nsitivity of the micrf219 receiver to a maximum of 45db for training the micrf219 receiver. this is done in order to recognize an intended transmitter. very often, a receiver needs to learn how to recognize a particular transmitter. it is important for the receiver not to learn the signal of a stray transmitter near by. the simplest solution is to turn down the receiver gain, so t he receiver only recognizes the transmitter at close range. the de-sense function is accessible only through serial programming. d mode: desense resh-hold, capaci an 750mv, a 15a current sink discharges capacitor. the voltage developed on t capacitor acts to adjust the gain of the mixer amplifier to compensate for rf input s variation. desense desense is a function e gc nd the if nal level se 0 d1 d2 0 no desense - default x x 1 6db desense 0 0 1 1 0 16db desense 1 0 1 30db desense 1 1 1 42db desense reference control ce and control sub- and 2) control logic 1, shdn micrf219 (figure 2) asic pierce crystal oscillator confi guration with negative resistance. though the micrf219 has build-in load capacitors for ator, the external load capacitors are still required for tuning it to the right frequency. r01 and r02 219 to connect the crystal to the reference oscillator. ncy can be calculated: f ref osc = f rf /(32 + 1.1/12) for 433.92 mhz, f ref osc = 13.52127 mhz. to operate the micrf219 with minimum offset, crystal frequencies should be specified with 10pf loading capacitance. there are 2 components in referen block: 1) reference oscillator through parallel inputs: sel0, sel reference oscillator the reference oscillator in the uses a b mos transconductor to provide the crystal oscill are external pins of the micrf reference oscillator crystal freque downloaded from: http:///
micrel micrf219 june 2011 9 m9999-060811 (408) 944-0800 v bias ro2 r ro1 c c figure 2. reference oscillator circuit edgedetector doutclk clk data edge pulses goodbit select 0, 2, 4, 8 good bits before wakeup d15 = 0 for normal operation d15 = 1 for auto polled operation squelchdisables do squelch decode windowcounter decode bad bits wakeup timer (300s) watchdog timer serial control register decode good bit count >=7 good <=4 good window decode 8 stage shift register auto poll clk sr d7 d15 d8 clkd sq qa1 bad bit returns to sleep r figure 3. autopoll, bi t-check block diagram downloaded from: http:///
micrel micrf219 june 2011 10 m9999-060811 (408) 944-0800 low the circ od. regis 14 to set the re used for control re u g, s bits he p for the programmed timer du data if it is present. is se ep peri the al re r of bits to be checked as good, before the receiver outputs data at the do pin. the bit-check window bits d9, d10, d11 must also be set to match the data period. the shortest default window time gives the least critical bit check action. for better discrimination, the window setting may be increased up towards the normal minimum time expected between data edges. note an this will result in all e device will remain in n the serial command go to sleep for the e to receive and check a again at do as soon f good rtz bits have seen, the device will gain for good bits after the sleep period. both high and low periods are nable the device e device to sleep. er a programmable rence frequency. if the next pulse edge falls within this window the bit is d and sufficient pulses have or a lack of pulses will ep for a further sleep od. squelch during normal operation, if four or less out of eight bit pulses are good, the do output is squelched. if good bit count increases to seven or more in any eight sequential bits, squelch is disabled allowing data to output at do pin. auto-polling the auto-poll block (figure 3) contains a oscillator that drives the sleep timer when the device is powered down. it also contains check whether the received bits are go polling is controlled by bit d15 in the serial conjunction with bits d12, d13, d power rest of uits to auto- ter, in sleep of the sed to device will stay awake until se rial bit d15 then set high again, to enable a further sle the sleep duty cycle may be controlled by of serial commands. auto-polling with bit-checking for auto-polling with bit-chec king, the seri bits d7and d8 need to be set for the numbe that a window time set longer th bits being tested as bad and th sleep polling mode. now, whe sets bit d15 high, the devic e will timer period and will then awak bits. the device will output dat as the programmed numbers o been received. if a bad bit is return to sleep mode and poll a timer period. bits d7, d8, a bit-check operation and bits d9, d10, d11 a adjust the sensitivity of the bit-check action. auto-polling without bit-checking for simple auto-polling without bit-checkin serial command with bit d15 set high and d13, d14 set to the desired sleep time. t will go to slee end a d12, device ration the t low, checked for each rtz bit. the device will continue to check bits until sufficient good bits e to wake up, or bad bits return th operation received pulse edges trigg window timer clocked by the refe then wake up to receive od. timing gister flagged as bad. detected good bits are counte the device will wake up on ce been received. two bad pulses cause the device to go to sle timeout peri downloaded from: http:///
micrel micrf219 june 2011 11 m9999-060811 (408) 944-0800 programm control register indiv d0 d1 e: desense serial interface register ing idual truth tables: d2 mod 0 x esense - defaul x no d t 1 0 desense 0 6db 1 1 0 16db desense 1 0 1 30db desense 1 nse 1 1 42db dese d3 d dwidth (at 433.92 hz 4 demod ban mode: m ) 0 0 5hz 162 1 0 3250hz 0 1 6500hz 1 1 ault 13000hz - def 5 d d 6 mode 1 0 slice level 30% 0 1 vel 40% slice le 1 1 0% - default slice level 5 0 0 el 60% slice lev setting d7 d8 mode: bit-check 0 0 bit-check 0 bits - default 1 0 bit-check 2 bits 0 1 bit-check 4 bits 1 1 bit-check 8 bits d9 d10 times (315 d11 bit-check window mode: mhz) set d3 to d3=1 d3=0 d3=1 d3=0 set d4 to d4=0 d4=0 d4=1 d4=1 0 0 393us, 785us 0 98us, 196us, 1 0 , 183us, 367us, 733us 0 92us 0 1 0 85us, 170us, 341us, 681us 1 1 0 79us, 157us, 314us, 629us 0 0 us, 577us 1 72us, 144us, 288 1 0 us, 525us 1 66us, 131us, 262 0 1 us, 473us 1 59us, 118us, 236 1 1 us, 420us 1 53us, 105us, 210 d9 d10 d11 bit-check window times (433.92mhz) mode: set d3 to d3=1 d3=0 d3=1 d3=0 set d4 to d4=1 d4=1 d4=0 d4=0 0 0 0 71us, 143us, 285us, 570us 1 0 0 67us, 133us, 266us, 532us 0 1 0 62us, 124us, 247us, 494us 1 1 0 57us, 114us, 228us, 457us 0 0 1 52us, 105us, 209us, 419us 1 0 1 48us, 95us, 190us, 381us 0 1 1 43us, 86us, 172us, 343us 1 1 1 38us, 76us, 152us, 305us d efau te 0, d11 is 111 d12 d13 d14 mode: sleep time lt sta d9, d1 0 0 0 10ms 1 0 0 20ms 0 1 0 40ms default 1 1 0 80ms 0 0 1 160ms 1 0 1 320ms 0 1 1 640ms 1 1 1 1280ms e: auto-poll d15 mod 0 awake C does not poll - default 1 auto-polls with sleep periods t to 0 d16 always set this bi uelch enable sq pin d17 mode: sq 0 0 squelch circuit enabled 0 1 squelch circuit disabled 1 0 squelch circuit disabled (default) 1 1 squelch circuit enabled the external pin sq can invert the setting of squelch ster bit d17. the external pin defaults high via an internal pull-up so the squelch is off with default d17 = 0 and on if d17 = 1. such bit logic is reversed if sq pin is tied to low (ground). d18 always set this bit to 1 on/off defined by regi d19 always set this bit to 0 downloaded from: http:///
micrel micrf219 june 2011 12 m9999-060811 (408) 944-0800 application information figure 4. q antenna and rf po rt connections figure 4 shows the schematic of the q configured for 433.29 mhz operation. figu r219bpf ation exam , 433.92mhz r219b 19 through figure 23 are pcb pictures. the qr21 int for the prototyping of an nna. the nal to be r verification. to use an antenna such a and solder the whip the pcb instead. a wire with 167mm (6.-inch) can be used as a tion if low cost antenna is needed. front-end band pass filter components l1 and c8 form the band-pass filter at front of the receiver. its purpose is to attenuate undesired outside band noise that degrades the receiver performance. it is calculated by the parallel resonance equation: f = 1/(2pi(sqrt l1c8)) table 2 shows the component values for most often l1 (nh) applic ple pf used frequencies. re 9bpf most tenna freq (mhz) c8 (pf) is a good starting po applications. current design offers two options: a wire antenna or 50 sma ante sma connection also allows an rf sig injected for test o s a 50 whip, remove the sma antenna in the hole on of 22awg substitu 315.0 6.8 39 390.0 6.8 24 418.0 6.0 24 433.92 5.6 24 table 2. front band-pass filter values for various frequencies this band-pass filter can be removed if the outside band noise does not cause a problem. the micrf219 has built-in image reject mixers which improve the selectivity significantly and reject outside band noise. downloaded from: http:///
micrel micrf219 june 2011 13 m9999-060811 (408) 944-0800 ape additional nd noise. tection for ed to find 50 ? . one using the mith chart easier via a software plot y, the user n for best hing point, ne needs to know the input impedance of the device. table 3 shows the pe of ic suggested matching val for the most of d frequencies. these sugge d value ay be t if the layout is exactly same he on here: f z devic low-noise amplifier input matching capacitor c3 and inductor l2 form the l sh matching network. the capacitor provides attenuation for low-frequency outside ba the inductor provides additional esd pro the antenna pin. two methods can be us these values that best matched near method is done by calculating the values equations below and the other is using a s utility. the latter is made input where components are added on. in this wa can see the impedance moving directio values of c8 and l1 toward to central matc like winsmith by noble publishing. to calculate the matching values, o input im dance the m rf219 and ues ten use ste s m differen not the as t e made req (mhz) c3 (pf) l2(nh) e ( ? ) 315 68 33 - j2 1.8 35 390 1.5 47 23 C j199 418 1.5 43 21 C j186 433.92 1.5 39 19 C j174 table 3. matching values for the most used frequencies equency of 433.92 mhz, the input impedance C j174.2 ? , then the matching components allel = b = .68msiemens 5k ? ; xp = 176.2 ? q = sqrt (rp/50 + 1) q = 5.831 xm = rp / q 82.98 ? resonance method for l-shape matching network lc = xp / (2pif); lp = xm / (2pif) l2 = (lclp) / (lc + lp); c3 = 1 / (2pifxm) l2 = 39.8nh c3 = 1.3pf with the smith first, one plots the input impedance of the device, (z = 18.6 C j174.2) ? @ 433.92mhz.(figure 5): for the fr is z = 18.6 are calculated by: equivalent par 1/z = 0.606 + j5 rp = 1 / re (b); xp = 1 / im (b) rp = 1.6 xm = 2 doing the same calculation example chart, would appear as follows, figure 5. devices input impedance, z = 19 C j174 ? second, one plots the shunt inductor (39nh) and the series capacitor (1.5pf) for the desired input impedance (figure 6). one can then see the matching leading to the center of the smith chart or close to 50 ? . downloaded from: http:///
micrel micrf219 14 m9999-060811 (408) 944-0800 crystal selection june 2011 figure 6. plotting of shunt inductor and series capacitor ed respectively) is the internal circuits. f load capacitance, +105oc temperature crels approved ( www.hib.com.br crystal y1 or y1a (smt or lead reference clock for all the device crystal characteristics of 10p 30ppm, esr < 50 ? , ? 40oc to range are desired. table 4 shows mi crystal suppliers such as or http://www.abracon.com/ ) and the oscillator of the micrf219 i oscillator. good ca re must be the printed circuit board. avoi the ground plane on the to refosc pins ro1 and ro2. wh in the layout, and the crystals the frequencies. s a pierce-type taken when laying out d long traces and place p layer close to the en care is not taken used are not verified, the oscillator may take longer time to start. time-to- be longer as well. in citance is too high (> the receiving central r the oscillator may not c = rf cal oscillator is low-side injection (32 13.52127mhz = 432.68mhz), that is, its frequency is below the rf carrier frequency and the image frequency is below the lo frequency. see figure 7. the product of the incoming rf signal and good-data in the do pin will some cases, if the stray capa 20pf). in this case, either frequency will offset too much o start. the crystal frequency is calculated by refos carrier/(32+(1.1/12)). the lo local oscillator signal will yield the if frequency, which will be demodulated by the detector of the device. figure 7. low-side injection local oscillator downloaded from: http:///
micrel micrf219 june 2011 15 m9999-060811 (408) 944-0800 sc (mh carrier (m n part number refo z) hz) hib part number abraco 9.81563 315.0 sa-9.815630-f-10-h-30-30-x a bls-9.81563mhz-10j4y 12.15269 90.0 3 sa-12.15 2690-f-10-h-30-30-x a bls-12.15269mhz-10j4y 13.02519 418.0 sa-13.02 5190-f-10-h-30-30-x a bls-13.025190mhz-10j4y 13.52127 433.92 sa-13. 521270-f-10-h-30-30-x a bls-13.521270mhz-10j4y 4. crystal requencies and vendor part numbers ata n fo ctly, it is dth o ilar to 7, pw2 is ed for the s found by foun , the ble 5. for 50% (100 therefore, a bandwidth of 13khz would be necessary (0.65 / 50sec). however, if this data am a h ty cycle, ba idt re ul hz (0 20sec). this exce the m band e odulator circuit. if one tries to excee the im ba idth, e pu would appear tc r w sel0 bw t pulse maxim baud 50% ycle table f demodulator bandwidth selection and d stream optimization jp1 and jp2 are the bandwidth selectio demodulator bandwidth. to set it corre necessary to know the shortest pulse wi encoded data sent in the transmitter. sim example of the data profile in the figure shorter than pw1, so pw2 should be us demodulator bandwidth calculation which i 0.65/shortest pulse width. after this value is setting should be done according to ta example, if the pulse period is 100sec, cycle, the pulse width w ill be 50sec (pw = 50%) / 100). r the f the the d duty sec strethe had ndw pulse p h requi would eriod wit d wo ed a 20% du d be 32.5k maximu then .65 / width of th dem d max um ndw th lse stre hed o ider. jp1 jp2 (hertz) (sec) for c sel1 demod. shortes um rate duty (hz) short short 1625 400 1250 open short 3250 200 2500 short open 6500 100 5000 open open 13000 50 10000 table 5. jp1 and jp2 setting, 433.92mhz other frequencies will have different demodulator bandwidth limits, which is derived from the reference oscillator frequency. table 6 and table 7 shows the limits for the other two most used frequencies. s j sel1 j de b (h shortest pulse (sec) maximum baud rate for 50% duty cycle (hz) el0 p1 p2 mod. w ertz) short short 1565 416 1204 open short 3130 208 2408 short open 104 4816 6261 open open 12523 52 9633 table 6. p1 an setting, 418.0mhz sel0 sel1 demod. (hertz) shortest pulse (sec) maximum baud rate for 50% duty cycle (hz) d jp2 jp1 jp2 bw short short 1170 445 1123 open short 2350 223 2246 short open 4700 111 4493 open open 9400 56 8987 table 7. jp1 and jp2 setting, 315mhz agc capacitor and data slicer threshold capacitor selection capacitors c6 and c4 th and c agc capacitors respectively providing a time base reference for the data pattern received. these capacitors are selected according to data profile, pulse duty cycle, dead time between two received data packets, and if the data pattern does has or not have a preamble. see figure 8 for example of a data profile. are c downloaded from: http:///
micrel micrf219 june 2011 16 m9999-060811 (408) 944-0800 figure 8. example of a data profile for best results, they should always be optimiz d for the data pattern u the baud rate increases, c itor s de se. e 8 s sugg ted values for manches ncoded data, 50% duty cycle. l0 1 sel jp2 de (hz) cagc e sed. as crea ter e the apac value tabl show es se jp 1 mod. bw cth short short 1625 100nf 4.7f open short 3250 47nf 2.2f short open 6500 22nf 1f open open 13000 10nf 0.47f table 8. suggested c th and c agc val jp3 and jp4 are jumpers selectable to h and used to configure the digital squelch when it is tied to high, there is no squelch ap the digital circuits and the do (data out) hash signal. when the pin is low, the do pi considerably reduced. it will have more or shown in the figure below depending upon ues igh or lo fun tio p pin n act les the o band noise. the penalty for using squelch is a d getting a good signal in the do pin. this means takes longer for the data to show up. the de dependent upon many factors such as rf intensity, data profile, data rate, c th and agc capacitor values, and outside band noise see figure 9 and figure 10. please note that squelch action is based on the bitcheck operation and may be optimized using the bitcheck window serial register w n. c lied to has a ivity is s than utside elay in that it lay is signal c setting. figure 9. data out pin with no squelch (sq = 1) figure 10. data out pin with other compo squelch (sq = 0) nents used are c5, which is a decoupling capacitor for the v dd line; r3 for the shutdown pin (shdn = 0, device is operation), which can be removed if that pin is connected to a microcontroller or an external switch; and r1 and r2 which form a voltage divider for the pin. one can force a voltage in this agc pin to purposely decrease the device sensitivity. special care is needed when doing this operation, as an external control of the agc voltage may vary from lot to lot and may not work the same in several devices. agc downloaded from: http:///
micrel micrf219 june 2011 17 m9999-060811 (408) 944-0800 ey are the pin has a enough for today. the rf signal determine signal-to-noise ratio of the rf link, crude range capacitor ve energy. e de c ion is en toggling ired f a tim o show up in the do pin. this time w dependent upon many things such as tempe the crystal used, and if ther e is an external os with faster startup time. see figure 11 and figu or time-to-good-data on both 433.92mhz and 31 versions. three other pins are worthy of comment. th do, rssi, and shutdown pins. the do driving capability of 0.4ma. this is good most of the logic family ics on the market rssi pin provides a transfer function of the intensity versus voltage. it is very useful to the estimate from the transmitter source and am demodulation, which requires a low c agc value. the shutdown pin (shdn) is useful to sa making its level close to v dd (shdn = 1), th not in operation. its dc current consumpt than 1a (do not forget to remove r3). wh from high to low, there will be a time requ device to come to steady-state mode, and data t vi e is less or the e for ill be rature, cillator re 12 5mhz figure 12. time-to-good-data a 315mhz at room te serial register programming programming the device is accompli of pins do and sclk. norm outputting data and needs to ma fter shutdown cycle, mperature shed by the use ally, d0 (pin 10) is switch to an input pin de by the start sequence, as shown at figure 13. high at the sclk pin tri-states the do pin, enabling the external drive into the do pin with an initial low level. the start sequence is completed by taking sclk low, then high while do is low, followed by taking do high, then low while sclk is high. the serial interface is initialized and ready to receive the programming data. bit time 1 bit time 0 do as output do input bits: sclk t1 t2 t6 t7 t3 t4 t5 t8 t9 d19 19 0 0 1 d18 d17 bit time 2 figure 11. time-to-good-data after shutdown cycle, 433.92mhz, room temperature figure 13. serial interface start sequence downloaded from: http:///
micrel micrf219 june 2011 18 m9999-060811 (408) 944-0800 the are (lsb d0) 1, and d2 e only bits t sequence if only the ence must s the stop ides d17) ended that q) be kept after the uence (as mode and reestablish the do pin as an output again. to do so, the in ch nges from high, then low again, followed by the scl of the programming bits are e kept as shown belo : t1 < 0.1s, time from sclk to convert do to input pin t6 > 0.1s, sclk high time t7 > 0.1s, sclk low time t2, t3, t4, t5, t8, t9, t10 > 0.1s bits are serially programmed starting with significant bit (msb = d19) if all bits programmed until the least significant bit for instance, if only the desense bits d0, d are being programmed, then these are th that need to be programmed with the star d2, d1, d0, plus the stop sequence. or, squelch bit d17 is needed, then the sequ be from start sequence, d17 through d0 plu sequence, making sure the other bits (bes are programmed as needed. it is recomm all parallel input pins (sel0, sel1, and s high when using the serial interface. programming bits are finished, a stop seq shown in figure 14) is required to end the most being = sclk pin is kept high while the do p low to a k pin made low. timing not critical, but should b w do pin as output do d1 1 0 1 do sclk t10 bit time 18 bit time 19 figure 14. serial interface stop sequence sclk frequency should be greater than 5khz to avoid automatic reset from internal circuitry. ing examples see figures 15 C 17. (channel 1 is the do pin, and channel 2 is the sclk pin). serial interface register load figure 15. all bits d19 through d0 = 0 figure 16. all bits d19 through d0 = 1 downloaded from: http:///
micrel micrf219 june 2011 19 m9999-060811 (408) 944-0800 figure 17. d19 = d18 = 1, d17 = d0 = 0 figure 18): nse 12 h 1 = 500sec. 500usec = bits. e is on checking for four 1 = 0, data rate is 1 khz, (500sec pulses), window set to 433sec (< 500 usec) d12 = d13 = 0, d14 = 1, sleep timer set to 160msec, that is, 4 bit is on and 160msec is off. d15 = 1, device is placed in autopoll d16 = 0, not used. always set to 0. d17 = 0, squelch is off d18 = 1, watchdog timer is off d19 = 0, no rssi offset from msb to lsb (see table 9): d19 d18 d17 d16 d15 d14 d13 d12 auto-poll programming example auto-poll example (see d0 = d1 = d2 = 0, no dese d3 = d4 = 0, demodulator bandwidth = 17 khz baud rate, pulse ertz, required demodulator bandwidth is 0.65/ 1300 hertz d5 = d6 = 1, slice level = 50% d7 = 0, d8 = 1, bit check = 4 this is the time th consecutive valid w e devic indows. d9 = d10 = 1, d1 0 1 0 0 1 1 0 0 d d7 d6 d5 11 d10 d9 d8 0 1 1 1 0 1 1 d4 d3 d2 d1 d0 0 0 0 0 0 table 9. auto-poll example bit sequence figure 18. autopoll example downloaded from: http:///
micrel micrf219 june 2011 20 m9999-060811 (408) 944-0800 t nloa ning s as g ne ger ) lon uld al be done with exhaustive range tests. make sure the individual ground connection has a dedicated via rather then sharing a few of ground points by a single via. sharing ground via will increase the ground path ld be solid and with no g ground plane on top ents. it normally adds which changes the materials as they are ically, fr4 or better he rf path should be avoid loops and ground and v dd lines wer circuits (such own sources of noise should be laid out as far as possible from the rf circuits. avoid unnecessary wide traces which would add more distribution capacitance (between top trace to bottom gnd plane) and alter the rf parameters. pcb considerations and layou figure 19 to figure 23 show the qr219bpf pcb layout. the gerber files provided are dow dable from micrel website and contain the remai layers needed to fabricate this board. when copying or making ones own boards, make the trace short as possible. long traces alter the matchin twork and the values suggested are no lon valid. suggested matching values may vary due to pcb variations. a pcb trace 100 mills (2.5mm g has about 1.1nh inductance. optimization sho ways inductance. ground plane shou sudden interruptions. avoid usin layer next to the matching elem additional stray capacitance matching. do not use phenolic conductive above 200mhz. typ materials are recommended. t as straight as possible to unnecessary turns. separate from other digital or switching po microcontrolleretc). kn figure 19. qr219bpf top layer figure 20. qr219bpf bottom layer downloaded from: http:///
micrel micrf219 june 2011 21 m9999-060811 (408) 944-0800 figure 21. qr219bpf top silkscreen layer figure 22. qr219bpf bottom silkscreen layer figure 23. qr219bpf dimensions (in inches) downloaded from: http:///
micrel micrf219 june 2011 22 m9999-060811 (408) 944-0800 qr219bpf bill of materials, 433.92mhz m reference rt ription qty. ite pa desc 1 ant1 2awg mm (6.6) 22awg wire 1 2 rigid wire 167 2 5 3 chip capacitor 1 c3 1.5pf 0v 060 3 4.7uf 6 5 chip capacitor 1 c4 .3v 080 4 0.1uf 1 03 chip capacitor 2 c6,c5 6v 06 5 5.6pf 5 pacitor 1 c8 0v 0603 chip ca 6 c10,c9 10pf 50 603 chip capacitor 2 v 0 7 jp1, jp2, r5, r6, r7 0ohm esistor 5 0603 chip r 8 r1, r2, jp3, jp (np) ip resistor, not placed 4 4 0603 ch 9 j1 con7 in connector 1 7 p 10 j2 unt sma connector 1 (np) edge mo 11 l1 h 5% 5%, 0603 smt inductor 1 24n 12 l2 ductor 1 39nh 5% 5%, 0603 smt in 13 r3 100kohm 0603 chip resistor 2 14 u1 micrf219ayqs micrf219 chip 1 15 y1 13.52127mhz crystal 1 f materials, 433.92mhz 2 pf bill o ials, m part scription qty. table 10. qr219bpf bill o qr 19b f mater 315mhz ite reference de 1 22awg ) 22awg wire 1 ant1 rigid wire 230mm (9.0 2 c3 1.8pf 5 apacitor 1 0v 0603 chip c 3 c4 4.7f 6 ip capacitor 1 .3v 0805 ch 4 c6,c5 0.1f 1 ip capacitor 2 6v 0603 ch 5 c8 6.8pf 5 03 chip capacitor 1 0v 06 6 c10,c9 50 3 chip capacitor 2 10pf v 060 7 jp1, jp2, r5, r6, r7 0 ? 0603 chip resistor 5 8 r1, r2, jp3, jp4 tor, not placed 4 (np) 0603 chip resis 9 j1 con7 7 pin connector 1 10 j2 (np) edge mount sma connector 1 11 l1 39nh 5% 5%, 0603 smt inductor 1 12 l2 68nh 5% 5%, 0603 smt inductor 1 13 r3 100k ? 0603 chip resistor 2 14 u1 micrf219ayqs micrf219 chip 1 15 y1 9.81563mhz crystal 1 table 11. qr219bpf bill of materials, 315mhz downloaded from: http:///
micrel micrf219 june 2011 23 m9999-060811 (408) 944-0800 package information qsop16 package type (aqs16) micrel, inc. 2180 fortune drive san jose, ca 95131 us tel +1 (408) 944-0800 fax +1 (408) 474-1000 web a http://www.micrel.com micrel makes no representations or warrant curacy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, ions and descriptions at any time without notice. no license, whether expre ss, implied, arising b r other wise, to any ctual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any expre ss or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchasers use or sale of micrel produc ts for use in life support applianc es, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2009 micrel, incorporated. ies with respect to t he ac specificat y estoppel o intelle downloaded from: http:///

▲Up To Search▲

Price & Availability of MICRF219AAYQS

	To Download MICRF219AAYQS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .